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Integrated Circuit Systems, Inc.
ICS954204
Programmable Timing Control HubTM for Mobile P4TM Systems
Recommended Application: CK410M Compliant Main Clock with Integrated LCD Spread Spectrum Clock. Output Features: * 2 - 0.7V current-mode differential CPU pairs * 5 - 0.7V current-mode differential SRC pair for SATA and PCI-E * 1 - 0.7V current-mode differential CPU/SRC selectable pair * 4 - PCI (33MHz) * 2 - PCICLK_F, (33MHz) free-running * 1 - USB, 48MHz * 1 - DOT, 96MHz, 0.7V current differential pair * 1 - REF, 14.318MHz * 1 - 0.7V current-mode differential LCD/SRC selectable pair. Key Specifications: * CPU outputs cycle-cycle jitter < 85ps * SRC outputs cycle-cycle jitter < 125ps * PCI outputs cycle-cycle jitter < 500ps * +/- 300ppm frequency accuracy on CPU & SRC clocks * +/- 100ppm frequency accuracy on USB clocks Features/Benefits: * Supports tight ppm accuracy clocks for Serial-ATA and SRC * Supports programmable spread percentage and frequency * * * Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning Supports undriven differential CPU, SRC pair in PD# for power management. CLKREQ pins to support SRC power management.
Pin Configuration
VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 *SELSRC_LCDCLK#/PCICLK_F1 Vtt_PwrGd#/PD VDD48 FSLA/USB_48MHz GND DOTT_96MHz DOTC_96MHz FSLB/TEST_MODE LCDCLK_SST/SRCCLKT0 LCDCLK_SSC/SRCCLKC0 SRCCLKT1 SRCCLKC1 VDDSRC SRCCLKT2 SRCCLKC2 SRCCLKT3 SRCCLKC3 SRCCLKT4_SATA SRCCLKC4_SATA VDDSRC
Functionality
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PCICLK2 PCI/SRC_STOP# CPU_STOP# FSLC/TEST_SEL REFOUT GND X1 X2 VDDREF SDATA SCLK GND CPUCLKT0 CPUCLKC0 VDDCPU CPUCLKT1
FS_C FS_B FS_A 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CPU MHz 266.67 133.33 200.00 166.67 333.33 100.00 400.00 200.00
SRC MHz 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00
PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33
REF MHz 14.318 14.318 14.318 14.318 14.318 14.318 14.318 14.318
USB MHz 48.00 48.00 48.00 48.00 48.00 48.00 48.00 48.00
DOT MHz 96.00 96.00 96.00 96.00 96.00 96.00 96.00 96.00
ICS954204
1. FS_C is a three-level input. Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FS_B and FS_A are low-threshold inputs. Please see the V IL_FS and V IH_FS
CPUCLKC1 specifications in the Input/Supply/Common Output Parameters Table for IREF correct values. GNDA VDDA CPUCLKT2_ITP/SRCCLKT7 CPUCLKC2_ITP/SRCCLKC7 VDDSRC CLKREQA#* CLKREQB#* SRCCLKT5 SRCCLKC5 GND
56-pin TSSOP *100Kohm Pull-Up Resistor
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ICS954204
Pin Description
PIN # PIN NAME 1 2 3 4 5 6 7 8 VDDPCI GND PCICLK3 PCICLK4 PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 PIN TYPE DESCRIPTION PWR PWR OUT OUT OUT PWR PWR I/O Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V Free running PCI clock not affected by PCI_STOP#. ITP_EN: latched input to select pin functionality 1 = CPU_ITP pair 0 = SRC pair Latched input select for LCD_ss/ SRCCLK output frequency: 0 = LCD, 1 = SRCCLK/ 3.3V free-running PCI clock output. Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be sampled. PD is an asynchronous active high input pin used to put the device into a low power state. The internal clocks, PLLs and the crystal oscillator are stopped. Power pin for the 48MHz output.3.3V 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V. Ground pin. True clock of differential pair for 96.00MHz DOT clock. Complement clock of differential pair for 96.00MHz DOT clock. 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table. True clock of LCDCLK_SS output / True clock of SRCCLK differential pair. Selected by SEL_LCDCLK# Complementary clock of LCDCLK_SS output / Complementary clock of SRCCLK differential pair. Selected by SEL_LCDCLK# True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. Supply for SRC clocks, 3.3V nominal True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Complement clock of differential SRC clock pair. True clock of differential SRC/SATA pair. Complement clock of differential SRC/SATA pair. Supply for SRC clocks, 3.3V nominal
9
*SELSRC_LCDCLK#/PCICLK_F1
I/O
10 11 12 13 14 15 16
Vtt_PwrGd#/PD VDD48 FSLA/USB_48MHz GND DOTT_96MHz DOTC_96MHz FSLB/TEST_MODE
IN PWR I/O PWR OUT OUT IN
17 18 19 20 21 22 23 24 25 26 27 28
LCDCLK_SST/SRCCLKT0 LCDCLK_SSC/SRCCLKC0 SRCCLKT1 SRCCLKC1 VDDSRC SRCCLKT2 SRCCLKC2 SRCCLKT3 SRCCLKC3 SRCCLKT4_SATA SRCCLKC4_SATA VDDSRC
OUT OUT OUT OUT PWR OUT OUT OUT OUT OUT OUT PWR
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ICS954204
Pin Description (Continued)
PIN # PIN NAME 29 30 31 32 GND SRCCLKC5 SRCCLKT5 CLKREQB#* Type PWR OUT OUT IN Pin Description Ground pin. Complement clock of differential SRC clock pair. True clock of differential SRC clock pair. Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are controlled. 0 = enabled, 1 = tri-stated Supply for SRC clocks, 3.3V nominal Complementary clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. True clock of CPU_ITP/SRC differential pair CPU_ITP/SRC output. These are current mode outputs. External resistors are required for voltage bias. Selected by ITP_EN input. 3.3V power for the PLL core. Ground pin for the PLL core. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Supply for CPU clocks, 3.3V nominal Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. Ref, XTAL power supply, nominal 3.3V Crystal output, Nominally 14.318MHz Crystal input, Nominally 14.318MHz. Ground pin. Reference Clock output 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values. TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table Stops all CPUCLK, except those set to be free running clocks Stops all PCICLKs and SRCCLKs besides the free-running clocks at logic 0 level, when input low PCI clock output.
33 34 35
CLKREQA#* VDDSRC CPUCLKC2_ITP/SRCCLKC7
IN PWR OUT
36 37 38 39
CPUCLKT2_ITP/SRCCLKT7 VDDA GNDA IREF
OUT PWR PWR IN
40 41 42 43 44 45 46 47 48 49 50 51 52
CPUCLKC1 CPUCLKT1 VDDCPU CPUCLKC0 CPUCLKT0 GND SCLK SDATA VDDREF X2 X1 GND REFOUT
OUT OUT PWR OUT OUT PWR IN I/O PWR OUT IN PWR OUT
53
FSLC/TEST_SEL
IN
54 55
CPU_STOP# PCI/SRC_STOP#
IN IN OUT
56 PCICLK2 *Pins 32 and 33 have pull-ups.
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Integrated Circuit Systems, Inc.
ICS954204
General Description
ICS954204 is a CK410M Compliant clock synthesizer. ICS954204 provides a single-chip solution for mobile systems built with Intel P4-M processors and Intel mobile chipsets. ICS954204 is driven with a 14.318MHz crystal and generates CPU outputs up to 400MHz. It provides the tight ppm accuracy required by Serial ATA and PCI-Express.
Block Diagram
REFOUT USB_48MHz X1 X2 XTAL OSC. FIXED PLL DIVIDER DOT_96MHz
PCICLK(5:2) PCICLK_F(1:0)
PROG. SPREAD MAIN PLL
SRCCLK(5:1) PROG. DIVIDERS CPUCLK2_ITP/SRCCLK7
CPUCLK(1:0) PCI/SRC_STOP# CPU_STOP# FSL(C:A) ITP_EN TEST_MODE VTT_PWRGD#/PD CLKREQ#A/B SDATA SCLK SelSRC/LCDCLK# CONTROL LOGIC
LCDCLKSS/SRCCLK0
IREF
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Integrated Circuit Systems, Inc.
ICS954204
General SMBus serial interface information for the ICS954204 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
ACK
Byte N + X - 1 N P Not acknowledge stoP bit
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ICS954204
Absolute Max
Symbol Parameter Min VDD_A 3.3V Core Supply Voltage VDD_In 3.3V Logic Input Supply Voltage GND - 0.5 Ts Storage Temperature -65 Tambient Ambient Operating Temp 0 Tcase Case Temperature Input ESD protection 2000 ESD prot human body model Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V C C C V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current IIL2 Low Threshold Input High Voltage Low Threshold Input Low Voltage Operating Supply Current Powerdown Current Input Frequency3 Pin Inductance1 Input Capacitance1 Clk Stabilization1,2 Modulation Frequency Tdrive_SRC Tdrive_PD Tfall_PD Trise_PD Tdrive_CPU_STOP VIH_FS SYMBOL VIH VIL IIH IIL1 CONDITIONS 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors 3.3 V +/-5% 3.3 V +/-5% IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX TSTAB Full Active, CL = Full load; all diff pairs driven all differential pairs tri-stated VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation SRC output enable after PCI_STOP de-assertion Differential output enable after PD# de-assertion PD# fall time of PD# rise time of CPU output enable after CPU_STOP de-assertion CPU_STOP fall time of CPU_STOP rise time of MIN 2 VSS - 0.3 -5 -5 -200 0.7 VSS - 0.3 275 64 5 14.31818 VDD + 0.3 0.35 400 70 12 7 5 6 5 1.3 30 1.8 33 10 300 5 5 10 5 5 5.5 0.4 1000 300 TYP MAX VDD + 0.3 0.8 5 UNITS V V uA uA uA V V mA mA mA MHz nH pF pF pF ms kHz ns us ns ns ns ns ns V V mA ns ns NOTES 1 1 1 1 1 1 1
3 1 1 1 1 1,2 1 1 1 1 2 1 1 2 1 1 1 1,3 1,3
Tfall_CPU_STOP Trise_CPU_STOP# VDD SMBus Voltage 2.7 VOL SDATA, SCLK @ IPULLUP Low-level Output Voltage IPULLUP VOL = 0.4 V Current sinking 4 TRI2C SCLK/SDATA (Max VIL - 0.15) to (Min VIH + 0.15) to SCLK/SDATA TFI2C (Max VIL - 0.15) Clock/Data Fall Time 1 Guaranteed by design, not 100% tested in production. 2 See timing diagrams for timing requirements. 3 Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
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Integrated Circuit Systems, Inc.
ICS954204
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER Current Source Output Impedance Voltage High Voltage Low Max Voltage Min Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL Zo VHigh VLow Vovs Vuds Vcross(abs) d-Vcross ppm CONDITIONS VO = Vx Statistical measurement on single ended signal using oscilloscope math function. Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 400MHz non-spread 400MHz spread 333.33MHz non-spread 333.33MHz spread 266.66MHz non-spread 266.66MHz spread 200MHz non-spread 200MHz spread 166.66MHz non-spread 166.66MHz spread 133.33MHz non-spread 133.33MHz spread 100.00MHz non-spread 100.00MHz spread 400MHz non-spread 400MHz spread 333.33MHz non-spread 333.33MHz spread 266.66MHz non-spread 266.66MHz spread 200MHz non-spread 200MHz spread 166.66MHz non-spread 166.66MHz spread 133.33MHz non-spread 133.33MHz spread 100.00MHz non-spread 100.00MHz spread VOL = 0.175V, VOH = 0.525V VOH = 0.525V VOL = 0.175V MIN 3000 660 -150 -300 250 750 0 790 0 390 50 -300 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.9135 5.9132 7.4128 9.9120 175 175 310 305 20 15 850 mV 150 1150 550 140 300 2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 2.5750 2.5983 3.0859 3.1010 3.8361 3.8550 5.0865 5.1116 6.0868 6.1170 7.5873 7.6250 10.0880 10.1383 700 700 125 125 mV mV mV ppm ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps % ps ps ps ps 1,3 1 1 1 1 1,2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1 1 1 1 1 1 TYP MAX UNITS NOTES 1 1,3
Average period
Tperiod
Absolute min/max period
Tabs
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle
tr tf d-tr d-tf dt3
Measurement from differential 45 50 55 wavefrom CPU(1:0), VT = 50% 20 100 tsk3 Skew CPU2_ITP, VT = 50% 90 150 Differential waveform tjcyc-cyc 35 85 Jitter, Cycle to cycle measurement, CPU(1:0) Differential waveform tjcyc-cyc 45 125 Jitter, Cycle to cycle measurement, CPU2_ITP 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
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Integrated Circuit Systems, Inc.
ICS954204
Electrical Characteristics - SRC 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER SYMBOL CONDITIONS MIN TYP MAX Current Source Output 1 VO = Vx 3000 Zo Impedance Statistical measurement on single VHigh 660 750 850 Voltage High ended signal using oscilloscope Voltage Low VLow -150 0 150 Measurement on single ended Vovs 790 1150 Max Voltage signal using absolute value. Min Voltage Vuds -300 0 Crossing Voltage (abs) Vcross(abs) 250 350 550 Variation of crossing over all 12 140 Crossing Voltage (var) d-Vcross edges see Tperiod min-max values Long Accuracy ppm -300 300 10.0030 100.00MHz non-spread Tperiod Average period 9.9970 10.0533 100.00MHz spread 100.00MHz non-spread 10.1280 Tabs 9.8720 Absolute min/max period 100.00MHz spread 10.1783 tr VOL = 0.175V, VOH = 0.525V Rise Time 175 308 700 tf VOH = 0.525V, VOL = 0.175V Fall Time 175 310 700 d-tr 30 125 Rise Time Variation d-tf Fall Time Variation 30 125 Measurement from differential dt3 45 50 55 Duty Cycle wavefrom tsk3 VT = 50% Skew 100 250 Measurement from differential tjcyc-cyc 40 125 Jitter, Cycle to cycle wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. UNITS mV mV mV mV ppm ns ns ns ns ps ps ps ps % ps ps Notes 1 1,3 1,3 1 1 1 1 1,2 2 2 1,2 1,2 1 1 1 1 1 1 1
Electrical Characteristics - LCD_SS 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER SYMBOL CONDITIONS MIN TYP Current Source Output 1 VO = Vx 3000 Zo Impedance Statistical measurement on single Voltage High VHigh 660 750 ended signal using oscilloscope Voltage Low VLow -150 0 Measurement on single ended Max Voltage Vovs 790 signal using absolute value. Min Voltage Vuds -300 0 Crossing Voltage (abs) Vcross(abs) 250 350 Variation of crossing over all Crossing Voltage (var) d-Vcross 12 edges tr VOL = 0.175V, VOH = 0.525V Rise Time 175 308 VOH = 0.525V, VOL = 0.175V tf 175 310 Fall Time d-tr 30 Rise Time Variation d-tf 30 Fall Time Variation Measurement from differential dt3 45 50 Duty Cycle wavefrom tsk3 VT = 50% Skew 100 Measurement from differential tjcyc-cyc 40 Jitter, Cycle to cycle wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. MAX UNITS 850 150 1150 550 140 700 700 125 125 55 250 125 mV mV mV mV ps ps ps ps % ps ps Notes 1 1,2 1,2 1 1 1 1 1 1 1 1 1 1 1
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Integrated Circuit Systems, Inc.
ICS954204
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS ppm see Tperiod min-max values Long Accuracy 33.33MHz output non-spread Tperiod Clock period 33.33MHz output spread 33.33MHz output non-spread Tabs Absolute min/max period 33.33MHz output spread VOH IOH = -1 mA Output High Voltage VOL IOL = 1 mA Output Low Voltage V OH = 1.0 V IOH Output High Current VOH = 3.135 V VOL = 1.95 V IOL Output Low Current VOL = 0.4 V Edge Rate Rising edge rate Edge Rate Falling edge rate tr1 VOL = 0.4 V, VOH = 2.4 V Rise Time VOH = 2.4 V, VOL = 0.4 V tf1 Fall Time dt1 VT = 1.5 V Duty Cycle VT = 1.5 V tsk1 Skew VT = 1.5 V tjcyc-cyc Jitter
1 2
MIN -300 29.9910 29.4910 2.4
TYP
MAX 300 30.0090 30.1598 30.5090 30.6598 0.55
-33 -33 30 1 1 0.5 0.5 45 1.37 1.6 38 4 4 2 2 55 500 500
50 50 95
UNITS ppm ns ns ns ns V V mA mA mA mA V/ns V/ns ns ns % ps ps
Notes 1,2 2 2 1,2 1,2 1 1 1 1 1 1 1 1 1 1 1 1 1
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Electrical Characteristics - 48MHz, USB
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Long Accuracy ppm see Tperiod min-max values Tperiod 48.00000 MHz output Clock period Tabs 48.00000 MHz output Absolute min/max period VOH IOH = -1 mA Output High Voltage IOL = 1 mA VOL Output Low Voltage VOH = 1.0 V IOH Output High Current VOH = 3.135 V VOL = 1.95 V IOL Output Low Current VOL = 0.4 V Rising edge rate Edge Rate Edge Rate Falling edge rate VOL = 0.4 V, VOH = 2.4 V tr1 Rise Time tf1 VOH = 2.4 V, VOL = 0.4 V Fall Time VT = 1.5 V dt1 Duty Cycle VT = 1.5 V tjcyc-cyc Jitter, Cycle to cycle
1 2
MIN -100 20.83125 20.4813 2.4 -29
TYP
MAX 100 20.83542 21.1854 0.55 -23
29 1 1 1 1 45 1.8 1.6 1.43 1.33 48 150 27 2 2 2 2 55 350
UNITS ppm ns ns V V mA mA mA mA V/ns V/ns ns ns % ps
Notes 1,2 2 1,2 1 1 1 1 1 1 1 1 1 1 1 1
Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
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Integrated Circuit Systems, Inc.
ICS954204
Electrical Characteristics - DOT, 96MHz 0.7V Current Mode Differential Pair
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, REF = 475 PARAMETER SYMBOL CONDITIONS MIN TYP MAX Current Source Output VO = Vx 3000 Zo1 Impedance Statistical measurement on single VHigh 660 790 850 Voltage High ended signal using oscilloscope VLow -150 0 150 Voltage Low Measurement on single ended Vovs 810 1150 Max Voltage signal using absolute value. Vuds -300 0 Min Voltage Vcross(abs) 250 400 550 Crossing Voltage (abs) Variation of crossing over all Crossing Voltage (var) d-Vcross 10 140 edges see Tperiod min-max values Long Accuracy ppm -100 100 Tperiod 96.00MHz 10.4135 10.4198 Average period Tabs Absolute min/max period 96.00MHz 10.1635 10.6698 tr VOL = 0.175V, VOH = 0.525V Rise Time 175 250 700 VOH = 0.525V, VOL = 0.175V tf 175 240 700 Fall Time d-tr 15 125 Rise Time Variation d-tf Fall Time Variation 30 125 Measurement from differential dt3 Duty Cycle 45 50 55 wavefrom Measurement from differential tjcyc-cyc 90 250 Jitter, Cycle to cycle wavefrom 1 Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz 3 IREF = VDD/(3xRR). For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50. UNITS mV mV mV mV ppm ns ns ps ps ps ps % ps Notes 1 1,3 1,3 1 1 1 1 1,2 2 1,2 1 1 1 1 1 1
Electrical Characteristics - REF-14.318MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS ppm see Tperiod min-max values Long Accuracy Tperiod Clock period 14.318MHz output nominal VOH IOH = -1 mA Output High Voltage IOL = 1 mA VOL Output Low Voltage VOH = 1.0 V IOH Output High Current VOH = 3.135 V Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
MIN -300 69.8270 2.4 -33
TYP
MAX 300 69.8550 0.4 -33
UNITS ppm ns V V mA mA mA ns ns % ps
Notes 1 1 1 1 1 1 1 1 1,2 1,2 1
IOL tr1 tf1 dt1 tjcyc-cyc
VOL = 1.95 V VOL = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
30 0.5 0.5 45 1 1 53 750 38 2 2 55 1000
Guaranteed by design and characterization, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
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ICS954204
SMBus Table: Output Enable Control Register Byte 0 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 35, 36 30, 31 26, 27 24, 25 22, 23 19, 20 17, 18 CPUCLK2_ITP/SRCCLK7 Enable SRCCLK5 Enable SRCCLK4/SATA Enable SRCCLK3 Enable SRCCLK2 Enable SRCCLK1 Enable SRCCLK0 Enable
Control Function Output Enable Reserved Output Enable Output Enable Output Enable Output Enable Output Enable Output Enable
Type RW
0 Disable (HiZ)
1 Enable
PWD 1 1 1 1 1 1 1 1
RW RW RW RW RW RW
Disable (HiZ) Disable (HiZ) Disable (HiZ) Disable (HiZ) Disable (HiZ) Disable (HiZ)
Enable Enable Enable Enable Enable Enable
SMBus Table: PLL1 Spread and Output Enable Control Register Byte 1 Pin # Name Control Function 8 Bit 7 PCI_F0 Enable Output Enable 14,15 Bit 6 DOT_96MHz Enable Output Enable 12 Bit 5 USB_48MHz Enable Output Enable 52 Bit 4 REFOUT Enable Output Enable Reserved Bit 3 41, 40 Bit 2 CPU_1 Enable Output Enable 44, 43 Bit 1 CPU_0 Enable Output Enable Spread Spectrum Mode Bit 0 Spread Control for PLL1 (CPU, SRC, PCIF, PCI)
Type RW RW RW RW RW RW RW
0 Disable Disable (HiZ) Disable Disable Disable (HiZ) Disable (HiZ) SPREAD OFF
1 Enable Enable Enable Enable Enable Enable SPREAD ON
PWD 1 1 1 1 1 1 0
SMBus Table: Output Enable Control Register Byte 2 Pin # Name 5 Bit 7 PCICLK5 4 Bit 6 PCICLK4 3 Bit 5 PCICLK3 56 Bit 4 PCICLK2 Bit 3 Bit 2 Bit 1 9 PCI_F1 Enable Bit 0 SMBus Table: SRC Free-Running Control Register Byte 3 Pin # Name 35, 36 Bit 7 SRCCLK7 Bit 6 30, 31 Bit 5 SRCCLK5 26, 27 Bit 4 SRCCLK4/SATA Bit 3 Bit 2 Bit 1 Bit 0 24, 25 22, 23 19, 20 17, 18 SRCCLK3 SRCCLK2 SRCCLK1 SRCCLK0
Control Function Output Enable Output Enable Output Enable Output Enable Reserved Reserved Reserved Output Enable
Type RW RW RW RW
0 Disable Disable Disable Disable
1 Enable Enable Enable Enable
RW
Disable
Enable
PWD 1 1 1 1 1 1 1 1
Control Function Free-Running Control Reserved
Type RW RW RW
0 Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running Free-Running
1 Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable Stoppable
PWD 0 0 0 0 0 0 0 0
Free-Running Control, not affected by PCI/SRC_STOP#
RW RW RW RW
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SMBus Table: DO T PD Mode an d O u tput Free-Running Contro l Reg ister Pin # Nam e Control Function Byte 4 Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 8 35, 36 40, 41 43, 44 PCICLK_F1 PCICLK_F0 CPUCLK_2 CPUCLK_1 CPUCLK_0 Free-Running Control, not affec ted by CPU_STO P# 14, 15 DO T _96MHz Power Down Mode Driv en in PD Reserved Free-Running Control, not affec ted by PCI/SRC_STO P#
Type
0
1
PWD 0 0 0
RW
Driv en
Hi-Z
RW RW RW RW RW
Free-Running Free-Running Free-Running Free-Running Free-Running
Stoppable Stoppable Stoppable Stoppable Stoppable
0 0 1 1 1
SMBus Table: O utput Mod e Control Register Byte 5 Pin # Nam e SRC(7:0) 17-20, 22-27, PCI/SRC_STO P# Driv e Bit 7 30, 31, 35, 36 Mode Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 35, 36 40, 41 43, 44 17-20, 22-27, 30, 31, 35, 36 35, 36 40, 41 43, 44 CPUCLK2_ITP CPU_STO P# Drive Mode CPUCLK_1 CPU_STO P# Driv e Mode CPUCLK_0 CPU_STO P# Driv e Mode SRC(7:0), 96MHz_SS PD Driv e Mode CPUCLK2_ITP PD Driv e Mode CPUCLK_1 PD Drive Mode CPUCLK_0 PD Drive Mode
Control Function Driv en in PCI/SRC_STO P# Driven in CPU_ST O P# Driven in CPU_ST O P# Driven in CPU_ST O P# Driv en in PD
Type RW RW RW RW RW
0 Driv en Driv en Driv en Driv en Driv en
1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
PWD 0 0 0 0 0
Driv en in PD Driv en in PD Driv en in PD
RW RW RW
Driv en Driv en Driv en
Hi-Z Hi-Z Hi-Z
0 0 0
SMBus Table: Test Mode, FS Readback, and PCI Stop# Co ntrol Register Pin # Nam e Control Function Byte 6 T est Mode Selection (Activ e only when B6b6 = Test Mode Selec tion Bit 7 1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Test Clock Mode Entry T est Mode Reserved Strength Prog Stop all PCI and SRC cloc ks Readback Readback Readback
Type RW RW
0 Hi-Z Normal O peration 1X O utputs Stopped -
1 REF/N Test Mode per B6b7 2X O utputs Activ e -
PWD 0 0 1 1 LATCHED LATCHED LATCHED
52 53 16 12
REF O UT STRENG TH PCI/SRC_STO P# F S_C FS_B FS_A
RW RW RW RW RW
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SMBus Table: Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Vendor & Revision ID Register Pin # Nam e RID3 RID2 RID1 RID0 VID3 VID2 VID1 VID0
Control Function REVISIO N ID
VENDO R ID
Type R R R R R R R R
0 -
1 -
PWD x x x x 0 0 0 1
SMBus Table: Clock Request Control Register Byte 8 Pin # Nam e Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 32 32 32 33 33 33 CLKREQ B# Control CLKREQ B# Control CLKREQ B# Control CLKREQ A# Control CLKREQ A# Control CLKREQ A# Control Control Register Nam e LCDCLK_SS3 LCDCLK_SS2 LCDCLK_SS1 LCDCLK_SS0
Control Reserved SRCCLK5 is controlled SRCCLK3 is controlled SRCCLK1 is controlled Reserved SRCCLK4 is controlled SRCCLK2 is controlled SRCCLK0 is controlled
Type RW RW RW RW RW RW
0 Not Controlled Not Controlled Not Controlled Not Controlled Not Controlled Not Controlled
1 Controlled Controlled Controlled Controlled Controlled Controlled
PWD 1 0 0 1 0 0
SMBus Table: LCDCLK_SS Byte 9 Pin # Bit 7 Bit 6 17,18 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 17, 18 17, 18 -
Control Bit S3 Bit S2 Bit S1 Bit S0 Select LCDCLK_SS/SRCCLK0 O utput Enable Enable SS Reserved
Type RW RW RW RW R RW RW
0
1
See LCDCLK_SS Frequency Select Table 2
PWD 0 1 1 1 1 1 0
*SEL SRC_LCDCLK# LCDCLK_SS/SRCCLK0 Enable LCDCLK_SS Spread Enable
LCDCLK Disable (HiZ) O FF
SRCCLK0 Enable ON
Table 2: LCDCLK_SS Frequency Select Byte9/ bit1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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S3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
S2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
S1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
S0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Pin 17/18 Spread % Spread Type MHz 100.00 100.00 0.8 Down 100.00 1 Down 100.00 1.25 Down 100.00 1.5 Down 100.00 1.75 Down 100.00 2 Down 100.00 2.5 Down 100.00 3 Down 100.00 +/-0.3 Center 100.00 +/-0.4 Center 100.00 +/-0.5 Center 100.00 +/-0.6 Center 100.00 +/-0.8 Center 100.00 +/-1.0 Center 100.00 +/-1.25 Center 100.00 +/-1.5 Center
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Table 3. Power-Up CLKREQ# Timing1
Parameter Power Valid to CLKREQ# Output Active TPVCRL (Fig. 1) SRC Clock Stablilzation Time from assertion TSRCSTBL of CLKREQ# (Fig. 1) 1 This timing is valid only after system clocks are stable. Symbol Min Max 100 800 Units s s
Power Stable to Device VPCIEXDEV TPVCRL CLKREQ# TSRCSTBL
SRCCLK Figure 1. Power-Up CLKREQ# Timing
Table 4. CLKREQ# Control Timing
Symbol TCRHoff TCRHon Parameter CLKREQ# De-asserted High to SRCCLK Parked (Fig. 2) CLKREQ# Asserted LOW to SRCCLK Active (Fig. 2) Min 0 0.4 Max Units s s
CLKREQ# SRCCLK Figure 2. CLKREQ# Control Timing
CLKREQ# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CLKREQ# pin is that the SRCCLK output will become active per the timing found in Table 4. The clock will become active in a glitch free manner, providing a full cycle at the time it becomes active. CLKREQ# - De-Assertion (transition from logic "0" to logic "1") The impact of asserting the CLKREQ# pin is that the SRCCLK output will become inactive setliing in the Tristate condition per the timing found in Table 4. The clock will become inactive in a glitch free manner.
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Integrated Circuit Systems, Inc.
ICS954204
Table 5: PCI_STOP# Functionality
PCI_STOP# 0 1 CPU Normal Normal CPU# Normal Normal SRC Normal
Iref*6 or Float
SRC# Normal Low
PCIF/PCI 33MHz Low
DOT Normal Normal
DOT# Normal Normal
USB 48MHz 48MHz
REF 14.318MHz 14.318MHz
Table 6: PD Functionality
PD 0 1 CPU Normal
Iref*2 or Float
CPU# Normal Float
SRC Normal
Iref*2 or Float
SRC# Normal Float
PCIF/PCI 33MHz Low
DOT Normal
Iref*2 or Float
DOT# Low Float
USB 48MHz Low
REF 14.318MHz Low
Table 7: Tristate CPU Clock Control Truth Table
Signal CPU[2:0] CPU[2:0] CPU[2:0] CPU[2:0] CPU[2:0] PD 10 0 0 0 1 1 CPU_STOP# 54 1 0 0 X X CPU_STOP Tristate BIT B5b[6, 5, 4] X 0 1 X X PD Tristate BIT B5b[2,1,0] X X X 1 0 NON-STOP OUTPUTS Running Running Running Driven @ IREF X2 Tristate STOPPABLE OUTPUTS Running Driven @ IREF X6 Tristate Driven @ IREF X2 Tristate
Table 8: Tristate SRC Clock Control Truth Table
Signal SRC SRC SRC SRC SRC PD 10 0 0 0 1 1 PCI/SRC_STOP# 55 1 0 0 X X PCI/SRC_STOP Tristate BIT B5b7 X 0 1 X X PD Tristate BIT B5b3 X X X 1 0 NON-STOP OUTPUTS Running Running Running Driven @ IREF X2 Tristate STOPPABLE OUTPUTS Running Driven @ IREF X6 Tristate Driven @ IREF X2 Tristate
Table 9: Tristate DOT Clock Control Truth Table
Signal DOT_96 DOT_96 DOT_96 PD 10 0 1 1 PD Tristate BIT B4b6 X 1 0 STOPPABLE OUTPUTS Running Driven @ IREF X2 Tristate
Table10: CLKREQ# Clock Control Truth Table
Signal SRC SRC SRC SRC SRC PD 10 0 0 0 0 1 PCI/SRC_STOP# 55 1 1 0 0 X CLKREQA# CLKREQB# 33, 32 0 1 0 1 X SELECTED OUTPUTS Running Tristate Tristate Stopped per B5b7 Stopped per B5b3
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ICS954204
N
c
L
INDEX AREA
E1
E
12 D
a
A2 A1
A
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 56
10-0039
-Ce
b SEATING PLANE
aaa C
D mm. MIN MAX 13.90 14.10
D (inch) MIN .547 MAX .555
Reference Doc.: JEDEC Publicat ion 95, M O-153
Ordering Information
ICS954204yGLFT
Example:
ICS XXXX y G Lx T
Designation for tape and reel packaging Lead Option (optional) LF = Lead Free LN = Lead Free Annealed Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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